In reply to Yordan Kamenov: This page was last edited on 19 November , at Sign up using Email and Password. Given trends in the semiconductor industry and the fact that both ICs are usually on the same board, lack of 5 V tolerance is probably very common, and chips that actually drive 5 V are probably even rarer. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of service , privacy policy and cookie policy , and that your continued use of the website is subject to these policies. Also this layer is the first lowest layer that is solely software based.

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This phy’s address should also match the phy address in the DTS. How did you decide these values? XX with your mac addresses.

Sign up using Facebook. In reply to Yordan Kamenov: Do rgii have another question? The management interface controls the behavior of the PHY. By using this site, you agree to the Terms of Use and Privacy Policy. In closing this technical guide, we will list the required RGMII delay configuration for each of the possible use cases. Often interfaces to the host processor over something like PCI Express for example.

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[1/2] Documentation: devicetree: clarify usage of the RGMII phy-modes – Patchwork

Stack Overflow works best egmii JavaScript enabled. Thank you very much. Expert points trichet christophe May 13, 1: Simply speaking, PHY chip is handling the physical signals, such as working mode, duplex, and negotiation. Apr 26, 7: There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree.

There are 32 addresses, each containing 16 bits.

If I do a reverse compile with ‘dtb’I can see that Petalinux generates this for both nodes:. You need to enable the gmii2rgmii driver, and use the binding below:.

While MAC chip is handling the data link layer, ethernet frame creation. If this post answers your question, please click the Verify Answer button below.

configure linux kernel for RGMII

Trademarks Privacy Policy Terms of Use. Please upgrade to a Xilinx. That makes kinda sence to me – as far as dts files make sense to ,inux Cadence GEM rev 0x at 0xeb irq 29 Source-synchronous clocking is used: I tested this with an ethernetfmc daughter card using the example designs here https: I having similar rgmi you have.


Ethernet family of linuz area network technologies. Ask a related question What is a related question? Do you have another question? We are glad that we were able to resolve this issue, and will now proceed to close this thread. Currently you should use ‘macb. Generally it defaults to ‘1’, but on some phy’s it can be changed using straps on the pcb for example.

Petalinux – dts node for GMII to RGMII ip – Community Forums

Another problem that I am experiencing is that eth0 is unable to generate the target frequency so I don’t have RX bytes in eth0 interface. Same for the local-mac-address. It’s likely that this is your problem.